This invention relates generally to a multiplication device using a semiconductor memory, e.g., ROM (Read-Only Memory).
In a conventional multiplication device with a ROM (hereinafter called the first prior technique), products about all combinations of multiplicands and multipliers are stored in the ROM, and using a multiplicand and a multiplier given as an address a corresponding product is read from the ROM. For example, on the one hand, when finding a product P of eight bits from a multiplicand F of four bits and a multiplier G of four bits by means of the first prior technique, a ROM that is accessed by 2.sup.4 .times.2.sup.4 =2.sup.8 addresses requires a storage capacity of 8.times.2.sup.8 bits (i.e., 256 bytes). On the other hand, when finding PRODUCT P of sixteen bits from a multiplicand X of eight bits and a multiplier Y of eight bits, a ROM that is accessed by 2.sup.8 .times.2.sup.8 =2.sup.16 addresses requires a storage capacity of 16.times.2.sup.16 bits (i.e., 2.sup.17 bytes).
Japanese Pat. Appln., published under Pub. No. 62-38938, discloses a ROM multiplication device (hereinafter called the second prior art technique). At least one of the numeric of a multiplicand given and the numeric of a multiplier given is divided into a plurality of partial numerics, and partial products about all combinations of the partial numerics of the multiplicand and the partial numerics of the multiplier are read from the ROM, and by performing a digit place alignment addition operation of these partial products, to find a product of the multiplicand and the multiplier. In comparison with the first prior art technique, the ROM storage capacity is reduced to 1/2.sup.9 in the case of finding PRODUCT P of sixteen bits from MULTIPLICAND X of eight bits and MULTIPLIER Y of eight bits. More specifically, in accordance with the second prior art technique, 8-bit MULTIPLIER X is, as is expressed by the following formula (1), is divided into two parts, that is, a 4-bit upper-order part X.sub.U and a 4-bit low-order part X.sub.L. EQU X=X.sub.U .times.2.sup.4 +X.sub.L ( 1)
Likewise 8-bit MULTIPLIER Y is, as is expressed by the following formula (2), is divided into two parts, that is, a 4-bit upper-order part Y.sub.U and a 4-bit low-order part Y.sub.L. EQU Y=Y.sub.U .times.2.sup.4 +Y.sub.L ( 2)
Here, P=X.times.Y=X.sub.U .times.Y.sub.U .times.2.sup.8 +X.sub.U .times.Y.sub.L .times.2.sup.4 +X.sub.L .times.Y.sub.U .times.2.sup.4 +X.sub.L .times.Y.sub.L, which is the formula (3). Four 8-bit partial products, i.e., X.sub.U .times.Y.sub.U, X.sub.U .times.Y.sub.L, X.sub.L .times.Y.sub.U, and X.sub.L .times.Y.sub.L, are read out of the ROM, and a digit place alignment addition operation of these partial products is performed according to the formula (3), to calculate PRODUCT P. If a single ROM is accessed four times, then the storage capacity of such a ROM is 8.times.2.sup.4 .times.2.sup.4 bits, or 2.sup.8 =256 bytes.
The first prior art technique has a simple configuration but represents the problem that it requires a large storage capacity. Additionally, for the case of the multiplication device incorporated into a floating-point arithmetic device, using a ROM with a less storage capacity is preferable to downsize multiplication devices.
The second prior art technique, when computing a product of a multiplicand of eight or more bits by a multiplier of eight or more bits, does not much contribute to reducing the ROM storage capacity.